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Multichannel Network Interface Controller for HDLC MUNICH32 PEB/F 20320 Version 3.3 Delta Sheet 12.97
This document describes the latest MUNICH32 (Version 3.3) in relation to the Version 3.2 and hence is a "Delta Sheet" which references the MUNICH32 User's Manual 01.96.
Siemens Semiconductor Group
(c) Siemens AG 1997. All Rights Reserved.
DS 3
Please note that any information contained in this publication may be subject to change. Siemens reserves the right to make changes to or to discontinue any product or service identified in this publication without notice. Please contact our regional offices to receive the latest version of the relevant information to verify, before placing orders, that the information being relied upon is current. Revision History: Previous Version: 05.97 Major Changes:
PEB/F 20320 PEF 20320
1 1.1
Upgrades of MUNICH32 V3.3 Package
MUNICH32 V3.3 is provided in both packages: P-MQFP-160-1 and P-TQFP-176. 1.2 Pin Configuration (top view) TQFP-176
N.C.19 N.C.18 A7 D7 VDD VSS A6 D6 A5 D5 VDD VSS VSS A4 D4 A3 D3 VDD VSS VSS A2 D2 BE0 D1 VDD VSS BE1 D0 BE2 VDD VSS BE3 W/R / R/W VDD VSS VSS DS / PCHK ADS / AS VDD VSS HOLD / BR BGACK / PM N.C.17 N.C.16 N.C.20 N.C.21 D8 A8 VSS VDD D9 A9 D10 A10 VDD VSS VDD D11 A11 D12 A12 VSS VDD D13 A13 VDD VSS D14 A14 VSS VDD D15 A15 D16 A16 VSS VSS VDD D17 A17 D18 A18 VSS VDD D19 A19 N.C.22 N.C.23 132 130 133 120 110 100 90 89 88
140 80
150 70
MUNICH32 PEB 20320
160 60
170 50
176 1
45 10 20 30 40 44
N.C.15 N.C.14 HLDA0 / BG0 HLDA / BG VDD VSS BERR READY/DSACK B16 I/M N.C.13 N.C.12 N.C.11 TCLK TSP TDATA AR TEST VSS VDD VSS SCLK RESET VSS VDD VDD JTEST3 JTEST2 JTEST1 JTEST0 N.C.10 CI4 CI3 CI2 CI1 CI0 RDATA RSP RCLK N.C.9 N.C.8 N.C.7 N.C.6 N.C.5
Index Marking
Semiconductor Group
N.C.1 N.C.2 D20 A20 VSS VDD D21 A21 D22 A22 VSS VSS VDD D23 A23 D24 A24 VSS VDD D25 A25 D26 A26 VSS VSS VDD D27 A27 D28 A28/DP0 VSS VSS VDD D29 A29/DP1 D30 A30/DP2 VSS VDD D31 A31/DP3 INT/INT N.C.3 N.C.4
2
12.97
PEB/F 20320 PEF 20320
1.3
Functional Upgrades
The RESET behaviour was changed between MUNICH32 V3.2 and MUNICH32 V3.3: MUNICH32 V3.3 performs a reset sequence in the first 12 SCL cycles after the leading edge of the 'RESET' signal. In order to meet this requirement the `RESET' pin has to be logical `0' until power as well as the clock system are in a stable condition. When being in this stable condition, the M32 is able to detect a rising edge of the `RESET' signal, which starts the internal `RESET' procedure. This sequence is performed independent of the duration of the 'RESET' signal. It is not allowed to activate an 'AR' during that reset sequence. In case of a power up RESET the device would not detect a rising edge of the RESET signal and would not execute a RESET. To avoid this situation, the RESET signal could be inverted in systems using a power up RESET. In this case the MUNICH32 V3.3 detects the trailing edge of RESET as 0 ->1 transition and performes the reset sequence as described above. In this case it is not allowed to give an AR during the first 12 SCL cycles after the trailing edge of RESET.
1.4
Electrical Characteristics
Note: The version number is identified in the Interrupt Information bits VN(3:1): these bits are '101' for version 3.3
The MUNICH32 V3.3 is available for the extended range of temperature: Ambient temperature ratings Parameter Ambient temperature under bias: PEB PEF Symbol TA TA Limit Values 0 to 70 -40 to 85 Unit C C
All other electrical characteristics are as specified in MUNICH32 User's Manual 01.96.
Semiconductor Group
3
12.97

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